What is CMOS Technology?New


CMOS technology is a predominant technology for manufacturing integrated circuits. CMOS stands for “Complementary Metal Oxide Semiconductor”. Microprocessors, batteries, and digital sensors among other electronic components make use of this technology due to several key advantages. This technology uses both NMOS and PMOS to realize various logic functions. Both N and P MOSFET channels are designed to have matching characteristics.

Before CMOS, PMOS and NMOS logic were widely used for implementing logic gates. PMOS was then replaced by the NMOS Technology, which used to be the standard IC fabrication technology. Initially, CMOS was slower and more expensive than NMOS. The main advantages of NMOS technology are simple physical process, functional density, processing speed and manufacturing efficiency. The main disadvantages of NMOS technology are its electrical asymmetry and static power dissipation. These drawbacks are minimized by using CMOS Technology. The main advantage of CMOS is the minimal power dissipation as this only occurs during circuit switching. This results in much better performance as it allows integrating more CMOS gates on an IC.


N-channel MOSFET consists of an N-type source and drain diffused on a P-type substrate. The majority carriers are electrons. When the applied voltage to the gate is high enough, the NMOS will conduct; otherwise, it will not. Since the majority carriers (electrons) travel faster than holes, NMOS are considered to be faster than PMOS.

NMOS Transistor
NMOS Transistor


P-channel MOSFET also has a Source and Drain diffused on a substrate. The Source is P-type while the substrate is N-type. The majority carriers are holes. PMOS will conduct when a low voltage is applied. When a high voltage is applied to the gate, the PMOS will not conduct.

PMOS Transistor
PMOS Transistor


Since CMOS technology uses both N-type and P-type transistors to design logic functions, a signal which turns ON a transistor type is used to turn OFF the other transistor type. This eliminates the need for pull-up resistors in favor of simple switches. In CMOS logic gates N-type MOSFETs are arranged in a pull-down network between the output and the low voltage supply rail (VSS or ground) while P-type MOSFETs are in a pull-up network between the output and the higher-voltage rail (often VDD). Thus, the N-type MOSFET will be ON when the P-type MOSFET is OFF, and vice-versa. For any input pattern, one of the networks is ON and the other is OFF.

CMOS Logic Gate
CMOS Logic Gate

CMOS advantages are high speed, low power dissipation, high noise margins in both states, and a wide range of source and input voltages (fixed source voltage).

CMOS Logic Gates

1) CMOS Inverter

The CMOS inverter is the simplest CMOS logic gate. The circuit consists of PMOS and NMOS FET. Input A serves as the gate voltage for both transistors while Y is the output.

CMOS Inverter
CMOS Inverter

The NMOS transistor has an input from VSS or ground and the PMOS transistor has an input from VDD. When the input (A) is low (<VDD, ~0 V, Logic 0), the NMOS is OFF while the PMOS is ON. VDD will appear at the output through the P-channel MOSFET path. Hence, there is output (Logic 1) with the circuit pulled up to VDD. When the input is high (~VDD, Logic 1), the PMOS is OFF while the NMOS is ON. The output is pulled down and is therefore low (Logic 0).


A 2-input NAND gate has two N-channel MOSFETs connected in series between Y (output) and GND and two P-channel MOSFETs connected in parallel between VDD and Y.


If either A or B is low (Logic 0), at least one of the NMOS transistors will be OFF. This breaks the path from Y to GND since the NMOS transistors are connected in series. But in this case at least one of the PMOS transistors is ON, completing a path from Y to VDD. This makes the output Y high (Logic 1). For Y to be low, both A and B should be high to ensure that both NMOS transistors are ON so that the path from Y to GND is complete. For all the other combinations of the inputs, Y will be high. The truth table of NAND logic gate is given below.

3) CMOS NOR Gate

In a 2-input NOR gate, the NMOS transistors are connected in parallel while the PMOS transistors are connected in series. When at least one of the inputs is high, at least one NMOS transistor pulls the output low. The output is only high when both inputs are low.

Complementary MOS NOR Gate
Complementary MOS NOR Gate

The truth table of NOR logic gate is given below.

CMOS is the dominant technology for IC fabrication mainly due to its efficiency in using electric power and versatility. The low-power design gives off minimal heat and is the most reliable among other existing technologies. The P-type and N-type transistors can be configured to form logic gates based on what the circuit design requires.

Authored By

Susie Maestre

Susie is an Electronics Engineer and is currently studying Microelectronics. She loves fictional novels, motivational books as much as she loves electronics and electrical stuffs. Some of her fields of interests are digital designs, biomedical electronics, semiconductor physics, and photonics.

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