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555 Timer - 4. Astable Multivibrator Configuration

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We’ve already covered the monostable and bistable operation of 555 timers in the previous tutorials. In this tutorial, we’ll be looking at the third configuration - the astable mode of the 555 timers. We’ll understand how to configure the timer in the astable mode and also take a look at its internal working. But before that, we encourage you to read “Introduction to 555 timers”, if you haven’t yet. That will surely help you to understand this tutorial in a better way.

An astable multivibrator is an electronic device with no stable state, i.e., it continuously oscillates between the two states HIGH and LOW. It is also known as a free-running multivibrator. As we saw in the previous tutorials, the monostable and the bistable multivibrator need an external trigger for their operation. But an astable multivibrator is different as it doesn't need any external trigger pulse. It has a built-in automatic triggering to switch between the states.

To make our 555 timer act as an astable multivibrator, we just need to connect two external resistors and a capacitor as shown in the below schematic. We don't need an external switch in this mode because the switching is automated.

Figure 1: Schematic of 555 timer as an Astable Multivibrator
Figure 1: Schematic of 555 timer as an Astable Multivibrator
  • The threshold pin (6) and trigger pin (2) are connected together. So at any instant, both the pins will receive the same input.
  • The external capacitor is connected between the ground and the common node of the threshold and trigger pin.
  • The discharge pin (7) is connected to a node between the two external resistors.
  • The reset pin (4) is pulled high to avoid accidental resets.
  • The control pin (5) can be used to change the threshold reference voltage of ⅔ VCC. We can apply external voltage on this pin and the reference voltage can be changed to values other than ⅔ VCC. However, in this tutorial, we’ll not be changing the reference voltage so the control pin is grounded via a 10nF capacitor.


Internal Operation as an Astable Multivibrator

The first step after connecting the external components per the schematic and applying the power supply is to reset the timer by applying a logic LOW on the reset pin (4) of the timer. This clears up any floating states in the circuit and the operation begins.

Figure 2: Capacitor voltage below ⅓ VCC sets the flip flop
Figure 2: Capacitor voltage below ⅓ VCC sets the flip flop

Initially, the capacitor is uncharged, i.e., at 0V. And as is visible from the schematic, the capacitor voltage is given as an input to both the trigger pin (2) and the threshold pin (6) of the timer. But the specialty of this configuration is that only one of the two comparators will output a logic HIGH at any given instant. So when the capacitor is at 0V, the upper comparator outputs a logic LOW because the non-inverting input of the upper comparator is connected to the capacitor at 0V and the inverting input is at ⅔ VCC. But if we look at the lower comparator, the non-inverting input is at ⅓ VCC and the inverting input connected to the capacitor is at 0V. So the non-inverting input is more than the inverting input, which changes the output of the lower comparator to logic HIGH, and the flip-flop is SET. Q becomes logic HIGH and QBAR becomes logic LOW. The output of the timer becomes logic HIGH. But right at that moment, something else takes place as well.

As you may recall from the tutorial on the monostable mode of the timer, the output QBAR is also given to the base of the discharge transistor of the timer. Because QBAR is logic LOW, the transistor stays in the off state and the capacitor starts charging to VCC through the resistors R1 and R2.

Figure 3: Capacitor starts charging from 0V towards ⅔ VCC
Figure 3: Capacitor starts charging from 0V towards ⅔ VCC

The voltage across the capacitor starts to increase gradually and it crosses the ⅓ VCC reference voltage of the lower comparator. This makes the output of the lower comparator logic LOW because the inverting input becomes more than the non-inverting input of the comparator. However, that doesn’t affect the charging of the capacitor because now both the inputs of the flip-flop are logic LOW which makes the flip-flop enter the memory state with Q as logic HIGH and QBAR as logic LOW, and that keeps the transistor in the off state, allowing the capacitor to keep charging.

The charging of the capacitor occurs through the two externally connected resistors R1 and R2. So the time taken by the capacitor to get charged up to ⅔ VCC depends on the values of both the resistors R1 R2, and the capacitor, and it is calculated by the following relation

So the duration for which our capacitor is charging, we get a logic HIGH as the output of the timer.

Figure 4: Capacitor voltage crosses ⅔ VCC and makes output logic LOW
Figure 4: Capacitor voltage crosses ⅔ VCC and makes output logic LOW

Eventually, the voltage across the capacitor crosses the ⅔ VCC level and this is where the behavior of the circuit changes. The voltage on the threshold pin of the timer, which is the non-inverting input of the upper comparator, becomes more than the reference voltage of ⅔ VCC. This makes the output of the upper comparator a logic HIGH, which in turn resets the flip-flop. So now the Q output of the flip-flop is logic LOW and the QBAR output is logic HIGH, and as a result, the output of the 555 timer is a logic LOW signal.

As you might’ve guessed by now, the moment when QBAR becomes a logic HIGH, the discharge transistor gets switched on. Now the capacitor has a path towards the ground through the resistor R2 and the transistor, and it starts discharging.

Figure 5: Discharging of the capacitor from ⅔ VCC towards ⅓ VCC
Figure 5: Discharging of the capacitor from ⅔ VCC towards ⅓ VCC

The capacitor voltage now falls below ⅔ VCC, making the inverting input of the upper comparator more than the non-inverting input, which results in the output of the comparator switching back to logic LOW. Once again, the flip-flop enters the memory state, this time with Q as logic LOW and QBAR as a logic HIGH and doesn’t stop the capacitor from getting discharged.

An important thing to note here is that the path for the discharging of the capacitor consists of only R2. So the time taken by the capacitor to get discharged to ⅓ VCC depends only on the value of resistor R2 and the capacitor and is calculated by the following relation

This means that the process of discharging of capacitor occurs at a faster rate than charging, as it experiences lesser resistance. The timer outputs a logic LOW for the duration that the capacitor is discharging.

Figure 6: Capacitor voltage drops below ⅓ VCC and makes output logic HIGH
Figure 6: Capacitor voltage drops below ⅓ VCC and makes output logic HIGH

Soon after, the voltage across the capacitor drops below the ⅓ VCC level. This is another event where the behavior of the timer changes. Now the non-inverting input of the lower comparator is at a higher voltage level than the inverting input. This changes the output of the lower comparator to a logic HIGH and sets the flip-flop. So now the Q output of the flip flop is once again a logic HIGH, while QBAR is a logic LOW. The output of the timer switches from logic LOW to logic HIGH.

At the same time, QBAR with logic LOW switches off the discharge transistor and the capacitor starts charging again towards ⅔ VCC.

Below is the complete waveform of the astable mode of the 555 timers along with the voltage across the capacitor. Initially, the voltage across the capacitor rises from 0V to ⅔ VCC, during which the timer outputs a logic HIGH. After reaching ⅔ VCC level, the capacitor starts discharging during which the timer outputs a logic LOW. Then it falls below ⅓ VCC and then the capacitor starts charging again. This process of charging up to ⅔ VCC and then dropping back to ⅓ VCC repeats itself over and over again until we remove the power supply from the circuit. That’s exactly what an astable multivibrator is.

Figure 7: Output waveform of the 555 timer in astable mode
Figure 7: Output waveform of the 555 timer in astable mode

As you may notice, the time taken by the capacitor to get charged and discharged is not the same, and that is why the output of the timer isn’t ON and OFF for equal durations. But the good thing is, that we can vary the time duration of charging and discharging, i.e. the duty cycle of the signal by changing the values of capacitors and resistors. This allows us to make use of the astable output of the timer for a variety of purposes, some of which are mentioned below:

  • For carrying out modulations of signals like frequency modulation and pulse position modulation.
  • Used as a square wave generator
  • The output of this mode is also used as clock signals for synchronization purposes
  • We can also generate PWM signals to control motors.

That’s it! With this, we’ve covered all the operating modes of the 555 timers. We hope that gave you a better insight into electronics and their internal working in general. We encourage you to get one of these 555 timers and explore the things you can do with it. It is a great learning experience for anyone.

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