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Electronics Reference

Field-Effect Transistors (AC Analysis)

FET Transconductance Factor

latex!encoded:base64,Z197bX0gPSB5X3tmc309XGZyYWN7XERlbHRhIFx0ZXh0cm17SX1fe1x0ZXh0cm17RH19fXtcRGVsdGEgXHRleHRybXtWfV97XHRleHRybXtHU319fT1nX3ttX3swfX0gXGxlZnQgWyAoIDEtXGZyYWN7XHRleHRybXtWfV97XHRleHRybXtHU319fXtcdGV4dHJte1Z9X3tcdGV4dHJte1B9fX0gXHJpZ2h0IF09Z197bV97MH19IFxzcXJ0e1xmcmFje1x0ZXh0cm17SX1fe1x0ZXh0cm17RH19fXtcdGV4dHJte0l9X3tcdGV4dHJte0RTU319fX1cOyxcO1w7XDtcO1w7Z197bV97MH19PVxmcmFjezJcdGV4dHJte0l9X3tcdGV4dHJte0RTU319fXtcbGVmdCB8IFx0ZXh0cm17Vn1fe1x0ZXh0cm17UH19IFxyaWdodCB8fQ==
 > FET Transconductance Factor

JFET or D-MOSFET Fixed-Bias Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9klatex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LWdfe219IFxsZWZ0ICggXHRleHRybXtyfV9kIFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccmlnaHQgKQ==latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgLWdfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAp
 > JFET or D-MOSFET Fixed-Bias Configuration (Unloaded)

JFET or D-MOSFET Self-Bias Configuration Bypassed RS (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9klatex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LWdfe219IFxsZWZ0ICggXHRleHRybXtyfV9kIFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccmlnaHQgKQ==latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgLWdfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAp
 > JFET or D-MOSFET Self-Bias Configuration Bypassed R<sub>S</sub> (Unloaded)

JFET or D-MOSFET Self-Bias Configuration Unbypassed RS (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcZnJhY3tcbGVmdCBbIDErZ197bX0gXHRleHRybXtSfV97XHRleHRybXtTfX0rXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtTfX19e1x0ZXh0cm17cn1fZH0gIFxyaWdodCBdfXtcbGVmdCBbIDErZ197bX0gXHRleHRybXtSfV97XHRleHRybXtTfX0rXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtTfX19e1x0ZXh0cm17cn1fZH0rXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtEfX19e1x0ZXh0cm17cn1fZH0gXHJpZ2h0IF19IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19latex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBcO1w7XDsgXGxlZnQgKCBcdGV4dHJte3J9X3tkfVxnZXEgMTBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBcO29yXDsgXHRleHRybXtyfV97ZH09XGluZnR5IFw7XE9tZWdhICBccmlnaHQgKQ==
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LVxmcmFje2dfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19fXsxK2dfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17U319K1xmcmFje1x0ZXh0cm17Un1fe1x0ZXh0cm17RH19K1x0ZXh0cm17Un1fe1x0ZXh0cm17U319fXtcdGV4dHJte3J9X3tkfX19latex!encoded:base64,XHRleHRybXtBfV97dn09LVxmcmFje2dfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19fXsxK2dfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17U319fSBcO1w7XDsgXGxlZnQgWyBcdGV4dHJte3J9X3tkfVxnZXEgMTAoXHRleHRybXtSfV97XHRleHRybXtEfX0rXHRleHRybXtSfV97XHRleHRybXtTfX0pIFxyaWdodCBd
 > JFET or D-MOSFET Self-Bias Configuration Unbypassed R<sub>S</sub> (Unloaded)

JFET or D-MOSFET Voltage-Divider Bias Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3sxfSBccGFyYWxsZWwgXHRleHRybXtSfV97Mn0=
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9klatex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LWdfe219IFxsZWZ0ICggXHRleHRybXtyfV9kIFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccmlnaHQgKQ==latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgLWdfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAp
 > JFET or D-MOSFET Voltage-Divider Bias Configuration (Unloaded)

JFET or D-MOSFET Common-Gate Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX09XHRleHRybXtSfV97XHRleHRybXtTfX0gXHBhcmFsbGVsIFxsZWZ0IFsgXGZyYWN7XHRleHRybXtyfV97ZH0rXHRleHRybXtSfV97XHRleHRybXtEfX19ezErZ197bX1cdGV4dHJte3J9X3tkfX0gXHJpZ2h0IF0=latex!encoded:base64,XHRleHRybXtafV97aX0gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtTfX0gXHBhcmFsbGVsIFxmcmFjezF9e2dfe219fSBcO1w7XDsgXGxlZnQgKCBcdGV4dHJte3J9X3tkfVxnZXEgMTBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccmlnaHQgKQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9klatex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09XGZyYWN7Z197bX0gXHRleHRybXtSfV97XHRleHRybXtEfX0rXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtEfX19e1x0ZXh0cm17cn1fZH19ezErXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtEfX19e1x0ZXh0cm17cn1fZH19latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgZ197bX0gXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
 > JFET or D-MOSFET Common-Gate Configuration (Unloaded)

JFET or D-MOSFET Source Follower Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPVx0ZXh0cm17cn1fZH0gXHBhcmFsbGVsIFx0ZXh0cm17Un1fe1x0ZXh0cm17U319IFxwYXJhbGxlbCBcZnJhY3sxfXtnX3ttfX0=latex!encoded:base64,XHRleHRybXtafV97b30gIFxjb25nICBcdGV4dHJte1J9X3tcdGV4dHJte1N9fSBccGFyYWxsZWwgXGZyYWN7MX17Z197bX19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17U319IFxyaWdodCAp
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09XGZyYWN7Z197bX0gXGxlZnQgKFx0ZXh0cm17cn1fe2R9IFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte1N9fSBccmlnaHQgKX17MStnX3ttfSBcbGVmdCAoXHRleHRybXtyfV97ZH0gXHBhcmFsbGVsIFx0ZXh0cm17Un1fe1x0ZXh0cm17U319IFxyaWdodCApfQ==latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgIFxmcmFje2dfe219XHRleHRybXtSfV97XHRleHRybXtTfX19ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtTfX0gXHJpZ2h0ICk=
 > JFET or D-MOSFET Source Follower Configuration (Unloaded)

E-MOSFET Drain-Feedback Bias Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX09XGZyYWN7XHRleHRybXtSfV97XHRleHRybXtGfX0rXGxlZnQgKCBcdGV4dHJte3J9X2QgXHBhcmFsbGVsIFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCApfXsxK2dfe219XGxlZnQgKCBcdGV4dHJte3J9X2QgXHBhcmFsbGVsIFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCApfQ==latex!encoded:base64,XHRleHRybXtafV97aX0gXGNvbmcgIFxmcmFje1x0ZXh0cm17Un1fe1x0ZXh0cm17Rn19fXsxK2dfe219XHRleHRybXtSfV97XHRleHRybXtEfX19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAp
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b309XHRleHRybXtSfV97XHRleHRybXtGfX0gXHBhcmFsbGVsIFx0ZXh0cm17cn1fe2R9IFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0R9fQ==latex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgIFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoXHRleHRybXtSfV97XHRleHRybXtGfX0sXDsgXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LWdfe219XGxlZnQgKCBcdGV4dHJte1J9X3tcdGV4dHJte0Z9fSBccGFyYWxsZWwgXHRleHRybXtyfV97ZH0gXHBhcmFsbGVsIFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAplatex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgLWdfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoXHRleHRybXtSfV97XHRleHRybXtGfX0sXDsgXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
 > E-MOSFET Drain-Feedback Bias Configuration (Unloaded)

E-MOSFET Voltage-Divider Bias Configuration (Unloaded)

Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3sxfSBccGFyYWxsZWwgXHRleHRybXtSfV97Mn0=
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9klatex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXHRleHRybXtSfV97XHRleHRybXtEfX0gXDtcO1w7IFxsZWZ0ICggXHRleHRybXtyfV97ZH1cZ2VxIDEwXHRleHRybXtSfV97XHRleHRybXtEfX0gXHJpZ2h0ICk=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dn09LWdfe219IFxsZWZ0ICggXHRleHRybXtyfV9kIFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccmlnaHQgKQ==latex!encoded:base64,XHRleHRybXtBfV97dn0gXGNvbmcgLWdfe219IFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFw7XDtcOyBcbGVmdCAoIFx0ZXh0cm17cn1fe2R9XGdlcSAxMFx0ZXh0cm17Un1fe1x0ZXh0cm17RH19IFxyaWdodCAp
 > E-MOSFET Voltage-Divider Bias Configuration (Unloaded)

JFET Self-Bias Configuration Bypassed RS (with RSIG and RL)

Without rdWith rd
Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==latex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b309XHRleHRybXtSfV97XHRleHRybXtEfX0=latex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9k
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1nX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHJpZ2h0ICk=latex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1nX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHBhcmFsbGVsIFx0ZXh0cm17cn1fe2R9IFxyaWdodCAp
 > JFET Self-Bias Configuration Bypassed R<sub>S</sub> (with R<sub>SIG</sub> and R<sub>L</sub>)

JFET Self-Bias Configuration Unbypassed RS (with RSIG and RL)

Without rdWith rd
Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==latex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3tcdGV4dHJte0d9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b309XGZyYWN7XHRleHRybXtSfV97XHRleHRybXtEfX19ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fX0=latex!encoded:base64,XHRleHRybXtafV97b30gXGNvbmcgXGZyYWN7XHRleHRybXtSfV97XHRleHRybXtEfX19ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fX0=
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1cZnJhY3tnX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHJpZ2h0ICl9ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fX0=latex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1cZnJhY3tnX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHJpZ2h0ICl9ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fStcZnJhY3tcdGV4dHJte1J9X3tcdGV4dHJte0R9fStcdGV4dHJte1J9X3tcdGV4dHJte1N9fX17XHRleHRybXtyfV97ZH19fQ==
 > JFET Self-Bias Configuration Unbypassed R<sub>S</sub> (with R<sub>SIG</sub> and R<sub>L</sub>)

JFET Voltage-Divider Bias Configuration (with RSIG and RL)

Without rdWith rd
Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3sxfSBccGFyYWxsZWwgXHRleHRybXtSfV97Mn0=latex!encoded:base64,XHRleHRybXtafV97aX0gPSBcdGV4dHJte1J9X3sxfSBccGFyYWxsZWwgXHRleHRybXtSfV97Mn0=
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b309XHRleHRybXtSfV97XHRleHRybXtEfX0=latex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9k
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1nX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHJpZ2h0ICk=latex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PS1nX3ttfSBcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHBhcmFsbGVsIFx0ZXh0cm17cn1fe2R9IFxyaWdodCAp
 > JFET Voltage-Divider Bias Configuration (with R<sub>SIG</sub> and R<sub>L</sub>)

JFET AC Analysis: Common-Gate Configuration (with RSIG and RL)

Without rdWith rd
Input Impedancelatex!encoded:base64,XHRleHRybXtafV97aX09XGZyYWN7XHRleHRybXtSfV97XHRleHRybXtTfX19ezErZ197bX1cdGV4dHJte1J9X3tcdGV4dHJte1N9fX0=latex!encoded:base64,XHRleHRybXtafV97aX09XGZyYWN7XHRleHRybXtSfV97XHRleHRybXtTfX19ezErXGZyYWN7Z197bX1cdGV4dHJte3J9X3tkfVx0ZXh0cm17Un1fe1x0ZXh0cm17U319fXtcdGV4dHJte3J9X3tkfStcbGVmdCAoIFx0ZXh0cm17Un1fXHRleHRybXtEfSBccGFyYWxsZWwgXHRleHRybXtSfV97XHRleHRybXtMfX0gXHJpZ2h0ICl9fQ==
Output Impedancelatex!encoded:base64,XHRleHRybXtafV97b309XHRleHRybXtSfV97XHRleHRybXtEfX0=latex!encoded:base64,XHRleHRybXtafV97b30gPSBcdGV4dHJte1J9X3tcdGV4dHJte0R9fSBccGFyYWxsZWwgXHRleHRybXtyfV9k
Voltage Gainlatex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19PWdfe219IFxsZWZ0ICggXHRleHRybXtSfV9cdGV4dHJte0R9IFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0x9fSBccmlnaHQgKQ==latex!encoded:base64,XHRleHRybXtBfV97dl97XHRleHRybXtMfX19IFxjb25nIGdfe219IFxsZWZ0ICggXHRleHRybXtSfV9cdGV4dHJte0R9IFxwYXJhbGxlbCBcdGV4dHJte1J9X3tcdGV4dHJte0x9fSBccmlnaHQgKQ==
 > JFET AC Analysis: Common-Gate Configuration (with R<sub>SIG</sub> and R<sub>L</sub>)
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